Hi.
I have a problem with a process which is based on CMOS technology. The
structure consists of a silicon substrate with heavy doping, coated with
thermal (gate) oxide - 85nm, then coated with a similar thickness of
Nitride. A Polysilicon electrode is placed on top of the Nitride. A further
2 Poly electrodes are subsequently patterned which overlap Poly 1 - CCD
device.
I am getting shorts between the first poly and the substrate. De-layering
and SEM inspections shows very small pinholes in the Nitride/Oxide (approx
200nm). These were made visible only by severe poly wet etching. This leaves
a square void under the pinhole.  It does not appear at any of the Poly 2 or
3 stages and so seems to rule out defects in the gate ox, which I would
expect to be randomly distributed.

Thanks