Hi you both,

the holes are generelly needed for the etching in silicon, and p-Si has
enough of them. As Dirk already said, (+) pole to n-epi and (-) pole to
etching solution.

I personally have a problem regarding that technics. We found by ECE a lot
of pores that go perpendicularly from the interface deeply into the epi. We
suppose a bad quality of the wafer or epi material, but do not know it
exactly. Maybe someone here has some experience with this. I hope to get
more information about the generation of such pores.

By the way, which approaches are usually used to check the quality of a
whole wafer incl. epi concerning defects or stress?

Cheers,
Anh Tuan


------------------------------------------------------------



                    Dirk Eicher
                    
                    mstadt.de>                 cc:
                    Sent by:                   Subject:     Re: [mems-talk]
Silicon Etch Stops [virus checked]
                    mems-talk-bounces@me
                    msnet.org


                    09.12.2004 18:30
                    Please respond to
                    General MEMS
                    discussion






To my knowledge the etch stop results from the pn-junction between the
n-layer and the p-wafer
when a reverse voltage is applied between the n-layer and an electrode
in the etching solution.
The etching stops at the pn-junction due to the lack of electrons as it
does for the boron etch stop.
The resulting structure thickness is defined by the thickness of the
epilayer.

Cheers, Dirk.


Roger Brennan wrote:

>Recently, I was told n-epi (silicon) could be used as the etch stop.  That
>is, the P substrate is etched away and the n-epi is left
>
>This is contrary to my understanding.  I thought P+ silicon was the only
>silicon etch stop.
>
>Thanks in advance,
>
>Roger Brennan
>
>
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