Dear members,

        I am currently designing a 5-stage ring oscillator with n-channel
thin film transistors ("NMOS"). I am trying to look for/learn the critical
transistor design parameters for the circuit to "ring", such as W/L ratios
for the drive and load transistors, the tolerance on parasitic overlap
capacitances, etc. Would you mind to enlighten me on some of these and
other design paremeters? I would also greatly appreciate your help if you
have some good references for me to look at. Thank you very much!


Yours sincerely,

Isaac Chan
University of Waterloo