Dear Badin,

the problem of bonding the silicon to the pyrex in the cavities is due to
the high electrical field when the voltage is applied. To avoid this effect
you need to ramp up the voltage slowly. The Suss Substrate Bonders SB6e/SB8e
allow this ramping up of all bonding parameters, certainly also the voltage
value.

Best Regards,
Margarete Zoberbier

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From: "Badin Damrongsak" 

I found a problem during an anodic bonding between thin silicon and pyrex
wafers using EVG520/620.

On pyrex wafer, it was etched about 2-3um depth to create the cavity which
is around 4mm in diameter. The pyrex was then bonded to a 200um thin silicon
wafer on which has no pattern.

The problem I have found is that the silicon area over the 3um gap cavity
was somehow bonded to the pyrex wafer. I have no clue where the problem is;
probably too high voltage, too high force, etc. Have you guys got any ideas
how to solve this issue? Please feel free to contact me.

The recipe of anodic bonding is as follows:
Temp = 380 degC
Force = 800 N    (probably too high, for thin silicon wafers)
V    = -1kV      (probably too high)
Time = 4 min

The above recipe works well for anodic bonding between std thickness silicon
wafer and pyrex.