I would say that depending on your wire bonding controls, that this is
the likely culprit.  A 1000 angstrom device and 3500 angstrom box is
quite thin and could easily be compromised by either Al or Au bonding if
the parameters are excessive...Cratering or a deep bond signature could
certainly break through this thin barrier.

Regards
Ken Smith


[email protected] wrote:

> Hello all,
>
> when I was making samples from SOI wafer, I found a relative small
> resistance(1 Mohm) between electrodes(200 micro*1mm) on top of device
> layer and substrate Si.
>
> from my analysis, there are two possibility:
>
> 1. the quality of SOI wafer(device layer 100nm, SiO2 Box 350 nm)
>
> 2. wire bonder, when I was doing wire bonder, it might punch through
> Au(100nm)/Si(100nm)/SiO2(350nm) down to the substrate.
>
> which one is more likely?