Hi Leo,

At CMU we use the upper aluminum interconnect layers of CMOS stacks as the
etch mask for the silicon release etch of our MEMS devices. The anisotropic
DRIE silicon etch depth in this process can be as much as 50 um. In general,
our MEMS chips also have integrated electronics and to date no one has
flagged a device performance or reliability issue arising from contamination
due to the etching of the aluminum mask. So metal mask for DRIE silicon etch
is not unheard of.

We use an STS ASE tool for the silicon release etch. The chamber has alumina
liners, but there are some exposed aluminum parts. However, proving to a Fab
manager that a metal mask for a silicon etch will not lead to chamber
contamination, or other unspecified adverse effects, has a very low
probability of success, so optimize your resist process.

For a 250 um, backside anisotropic silicon etch, I'm using 4.2 um of AZ4210.
The maximum baking temperature is 90 deg C and the resist pattern is intact
after etch using a 10:1 SF6:O2 ratio during etch and C4F8 passivation.

Good luck and regards,

Peter

-----Original Message-----
From: [email protected] [mailto:[email protected]]
On Behalf Of Xiaoguang "Leo" Liu
Sent: Thursday, August 31, 2006 5:24 PM
To: General MEMS discussion
Subject: [mems-talk] Metal mask for DRIE

Dear all
I'm trying to do a  through wafer etch (550um) using silicon Deep RIE.
I've tried with the AZ9260 photoresist. However, the reflow of the
photoresist after hard bake makes the etching profile non-uniform.

Does anybody know if metal can be used in the DRIE process. I've heard
that people have done 2mm etching using Ni as a mask. However, our
staff here says metal is not allowed in the chamber. It would be great
if anybody could give some references on that. Thanks a lot

Leo