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MEMSnet Home: MEMS-Talk: RIE of SOI wafers
RIE of SOI wafers
2008-12-04
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2008-12-05
Morten Aarøe
2008-12-05
Jie Zou
2008-12-06
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2008-12-06
Dean Hopkins
2008-12-06
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2008-12-06
[email protected]
2008-12-07
Jie Zou
2008-12-08
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2008-12-09
[email protected]
RIE of SOI wafers
[email protected]
2008-12-04
Hello all,

I have just started working with SOI wafers and I just come across my
first frustrating problem:

I can't etch with our RIE two SOI wafers, and I have to.
Strange, but I etched other SOI wafers (with different device layer
thickness) and bare silicon wafers without problems with the same RIE
recipe.

But, when I try with these two wafers, the etching rate decreases as
much as ten times, and then the resist thickness is not enough to etch
the device layer.

The device layer is 300 nm thick of silicon.

I tested different parameters:

SF6: from 7 to 26 sccm (and also with small amounts of O2 and Ar, but
they decreased the selectivity),
RF Power: from 20 to 75 W,
Pressure: from 0.02 mbar to 0.2 mbar (= 15-150 mtorr).
Resist: 500 nm ZEP520 (I also tried PMMA, but the selectivity was worst)

In the deepest etch, I only get 200 nm etch before the resist
disappears.

The recipe should work for 300 nm Silicon, so I started to suspect that
either something strange happens with the wafers, or I am missing
something important in the procedure.

Until now I worked with the wafers without cleaning (just as clean as
they come from the box). Do you think that this could be the problem?
Should I clean them with acid before processing? How?
Do you think that it is possible that a thin film of oxide, or
whatever, in the surface of the wafer could be the problem? Or do you
think that the cause could be another reason?

I would appreciate any suggestion, because I really need to etch these
wafers.

Thanks,
Jose Marques
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