Another suggestion is to ask people who are making photonic crystals using SOI,
there is a big community.  I know one in EE in Delaware, you check his papers,

-Mehmet

------Original Message------

From: [email protected]
Sender: [email protected]
To: [email protected]
ReplyTo: General MEMS discussion
Subject: Re: [mems-talk] RIE of SOI wafers
Sent: Dec 6, 2008 5:25 AM

Dear Morten,

Thanks for the suggestion.

Unfortunately, in my design there are features 300 nm wide, and the
thickest resist layer I can use to pattern them with the e-beam is 500
nm of ZEP.

The problem is that 500 nm resist should resist the etch to drill 300 nm
of silicon (indeed, it does it with other wafers, but not with these two
"problematic" wafers).

So, I started to think that maybe there is something on/in the
device layer that delays the etch (oxide? too much dopant?...), and I
would like to know if somebody has
had a similar experience, or an idea about the reason for this.

Best regards,
Jose