Jose:

What type of DRIE is this?  We had similar problems while using Alcatel where
there was a clamp from the top and then due to BOX layer could not bias the
silicon.  One suggestion, we deposited metal on the backside of the wafer (We
had SOI on glass, worst than you).  You can email Carlos Mastrangelo at Utah, he
may recall more,

best,

-Mehmet

------Original Message------

From: [email protected]
Sender: [email protected]
To: [email protected]
ReplyTo: General MEMS discussion
Subject: Re: [mems-talk] RIE of SOI wafers
Sent: Dec 6, 2008 5:25 AM

Dear Morten,

Thanks for the suggestion.

Unfortunately, in my design there are features 300 nm wide, and the
thickest resist layer I can use to pattern them with the e-beam is 500
nm of ZEP.

The problem is that 500 nm resist should resist the etch to drill 300 nm
of silicon (indeed, it does it with other wafers, but not with these two
"problematic" wafers).

So, I started to think that maybe there is something on/in the
device layer that delays the etch (oxide? too much dopant?...), and I
would like to know if somebody has
had a similar experience, or an idea about the reason for this.

Best regards,
Jose