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MEMSnet Home: MEMS-Talk: RIE of SOI wafers
RIE of SOI wafers
2008-12-04
[email protected]
2008-12-05
Morten Aarøe
2008-12-05
Jie Zou
2008-12-06
[email protected]
2008-12-06
Dean Hopkins
2008-12-06
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2008-12-06
[email protected]
2008-12-07
Jie Zou
2008-12-08
[email protected]
2008-12-09
[email protected]
RIE of SOI wafers
Jie Zou
2008-12-07
Hi Mehmet,

Did you DRIE the device layer or the substrate? If the Alcatel put a clamp
from the top, then it should bias the device layer well, and the etching
into the device layer is good. Am I understanding right?

All the best,
Jie

On Sat, Dec 6, 2008 at 2:09 PM,  wrote:

> Jose:
>
> What type of DRIE is this?  We had similar problems while using Alcatel
> where there was a clamp from the top and then due to BOX layer could not
> bias the silicon.  One suggestion, we deposited metal on the backside of the
> wafer (We had SOI on glass, worst than you).  You can email Carlos
> Mastrangelo at Utah, he may recall more,
>
> best,
>
> -Mehmet
>

*  Zou Jie (Jay)
*  Department of Physics
*  University of Florida
*  Tel: +1-352-846-8018
*  Email: [email protected]
*  Homepage: http://plaza.ufl.edu/zoujie/
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