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MEMSnet Home: MEMS-Talk: RIE of SOI wafers
RIE of SOI wafers
2008-12-04
[email protected]
2008-12-05
Morten Aarøe
2008-12-05
Jie Zou
2008-12-06
[email protected]
2008-12-06
Dean Hopkins
2008-12-06
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2008-12-06
[email protected]
2008-12-07
Jie Zou
2008-12-08
[email protected]
2008-12-09
[email protected]
RIE of SOI wafers
[email protected]
2008-12-08
Dear all,

Thank you for the suggestions.

I will connect the device layer to the electrode to check if the etching
rate of the silicon increases (I just hope the etching rate of the
resist will not increase also, because then the selectivity would not
improve).

About the RIE (not DRIE, unfortunately), I can't fix the bias (it is
done with the other parameters).

The wafer is slighly doped, and the etching rate is ten times slower
than for the bare silicon. I know that in the case of wet etch,
sometimes small amounts of dopant change the results drastically. But in
the case of plasma etching, Is such a large difference possible due
only to the dopant?

About the surface: Can I assume that the wafers are ready to use from
the box? Or do you think that it would be a good idea to clean them with
HF, just in case?

Dear Mehmet, I share Jie's question: Which side do you metalize to etch
which side?

Best regards,
Jose

> Hi Mehmet,
>
> Did you DRIE the device layer or the substrate? If the Alcatel put a
> clamp
> from the top, then it should bias the device layer well, and the
> etching
> into the device layer is good. Am I understanding right?
>
> All the best,
> Jie

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