Jose:

Wafers should be clean, but will always be good to do a piranha clean and a
short BOE dip.
My device is published in 2004 JMEMS, 3D Micro mirrors...
Long time ago.  I was etching si which was bonded to a glass layer.  This piece
was 4cmx4cm, hence I put it onto another Si wafer which the clamp came down.
Etch stopped shortly.  Then we deposited metal on the backside of glass (where
the etched Si was bonded to) which got eletrically connected to the clamp and
fixed the problem,

-Mehmet


-----Original Message-----
From: 

Date: Mon, 8 Dec 2008 17:12:34
To: 
Subject: Re: [mems-talk] RIE on SOI wafers


Dear all,

Thank you for the suggestions.

I will connect the device layer to the electrode to check if the etching
rate of the silicon increases (I just hope the etching rate of the
resist will not increase also, because then the selectivity would not
improve).

About the RIE (not DRIE, unfortunately), I can't fix the bias (it is
done with the other parameters).

The wafer is slighly doped, and the etching rate is ten times slower
than for the bare silicon. I know that in the case of wet etch,
sometimes small amounts of dopant change the results drastically. But in
the case of plasma etching, Is such a large difference possible due
only to the dopant?

About the surface: Can I assume that the wafers are ready to use from
the box? Or do you think that it would be a good idea to clean them with
HF, just in case?

Dear Mehmet, I share Jie's question: Which side do you metalize to etch
which side?

Best regards,
Jose