Hi Jason,

It seems that the bonding process they used to manufacture your SOI
wafers is what to blame.  I've used many bonded SOI wafers in the past
to build released MEMS out of the device layer without such issues.
Annealing may be tricky though.  You mentioned that you had fix-fix
designs, which would require both stress and stress concentration to be
relieved.  I'd attempt a design of experiment at around 900C (above the
re-crystallization temperature for Si and viscous flow temperature for
SiO2) for a minimum of 1 hour.  However, unless you're stuck with these
wafers or you're really into solving the stress problem, I'd try to
communicate with the vendor for a return or exchange.

Hope this helps.
Trent

[email protected] wrote:
> Hi Michael, the devices are single layer structures, and they should
> not have an oxide layer: the observation of buckling and curvature was
> made immediately (2 mins) after the SiO2 etch to release the
> structures (15 mins in 50% HF), which would have stripped any oxide.
> The process was entirely based on photoresist masking and wet etching,
> so I don't think it can be any other layer causing the stress issues.
>
> Jason Milne