Hi everyone,

I am attempting to electroplate copper structures on to CMOS die.  Low
loss electrical contact must be made between the electroplated copper
and the CMOS top metal layer, an aluminum alloy, by way of openings in
the CMOS passivation layer.  These openings are created by the CMOS fab
(ie. they are standard pad openings).  Unfortunately, I am measuring
significantly more resistance between the CMOS Al and the Cu then
expected.  I believe the problem is incomplete removal of Al oxide.

Currently in my process I ion mill the CMOS (argon etch 20min at an
assumed 5nm/min) and then deposit Ti(10nm)/Cu(160nm) seed layers for
electroplating.  I then remove the sample from the chamber, pattern the
structures, and plate Cu(>5um).  Prior to plating I dip the sample in
H2SO4 for a few seconds to remove Cu oxide.

If anyone has worked with a similar process, I would greatly appreciate
suggestions concerning possible sources of the high loss and possible
ways to mitigate them.

Cheers,
Ken