Dear colleagues:
Awhile ago I sought suggestions on fabrication processes for a device
containing three levels of etched features on a silicon wafer. The features
include basins of about 10 micron deep, trenches of about 50 micron wide and
50 micron deep, and narrow through-holes of 15 micron wide and 120 micron
long (I missed the dimensions of the through-holes in my original inquiry).
I received many very helpful responses. In the following I attach the
responses to share them with the community. Thanks for those who spent
their precious time in providing the suggestions.
Xiaochuan Zhou
Xeotron Corporation
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Dr. Zou,
We are probably all wondering just how narrow your through etches have
to be.
If you can use a dry etcher (DRIE), then I think Brian Hubert's
suggestion will work well. In my experience you can spin resist over
105m dry-etched deep cavities. However, over anisotropically wet etched
features it will be difficult to spin, due to the very sharp corners.
Another "trick" are so-called nested masks. Basically, Chris Foreman
and Ralf G. Longwitz suggested this technique with increasing thickness
of oxide in and resist, respectively. Now, that can be tricky,
especially if your etching process eats away the mask as well.
Instead, one can use different masking layers. For example, oxide and
resist for dry etching.
- deposit 1st layer (oxide) and pattern it (for 2nd etch)
- deposit and pattern 2nd layer (resist) for (1st etch)
Then you etch the 2nd (deeper) etch a little, strip the resist and etch
both patterns. It is somewhat tricky to get the deeper etch depth
right, if the etch rate is not constant. This is true in plasma systems
with loading, and also the etch chemistry does change when masking
layer changes. So you need to find the respective etch rates for each
scenario.
Wet etching is more straightforward since the etch rate is constant.
Possible masking layers are nitride and oxide, each of which can be
selectively patterned and removed.
There is even a trick to etch each cavity to its final depth
individually:
- deposit nitride, pattern 2nd etch inverse (dark field)
- deposit oxide, pattern 1st etch
- etch 1st pattern
- thermally oxidize, this protects the just etched cavity (the region
under the nitride doesn't get oxidized)
- strip nitride (phosphoric acid), this leaves the oxide mask intact
etch 2nd pattern
I just learned about this from Martin Schmidt, and MIT has a patent on
this.
This nested mask approach can be extended to more steps, if you find
more masking layers that can be selectively patterned and removed, e.g.
metals.
Good luck,
Alexander Hoelke, Ph.D.
Massachusetts Institute of Technology
Microsystems Technology Laboratory
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I have developed a process for precisely the kind of patterning for deep-
etched features that you are talking about that I have used very
successfully. Details of the process have been published in the Hilton
Head '98 proceedings, and will appear in the September issue of JMEMS.
Steps are :
Grow oxide and pattern
Spin on thick resist and pattern
First etch
Strip of oxide
Second etch
If you need a third wafer through etch, you can do backside patterning.
This makes the process of making complex devices in Si quite easy and
overcomes the whole two resist or patterning on etched features headache.
If would like more details, feel free to contact me.
N. Rajan
Case Western Reserve University
10900 Euclid Ave
Cleveland, OH 44106
e-mail: [email protected]
Ph:216-3681037
__________________________________________________
I have only a two level process. You may use a similar method to solve your
problem.
I have to etch through a wafer and form some 50um groove on the same side of
a wafer.
The solution was to first grow an oxide, pattern, nitride,pattern
nitride,wet etch the oxide
thru the window in the nitride, KOH thru hole, remove nitride, KOH the
groove.
You may use a similar method with one more masking film. I used oxide and
nitride for
masking. Maybe you can add nickel as the third masking film.
Cheers!
TK
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Dear Dr. Zhou,
The problem you describe is a common problem in MEMS when dealing
high-aspect ratio microstructures, namely the uniform coating of photoresist
over severe topography.
Recently, we have published an article in the magazine "High-Density
Interconnect" that discusses this issue and presents results on a patented
spray coating technique developed by Electronic Visions, Inc. called
OmniSpray technology. This spray coating techique was specifically developed
for MEMS applications.
For a copy of this article T. Luxbacher and A. Mirza, High-Density
Interconnect, May 1999, Vol 2, No 5, p36-41 please e-mail [email protected]
(mailto:[email protected] )
Regards,
Andy Mirza
Technology Manager
Electronic Visions, Inc.
3701 E. University Drive
Ste. 300
Phoenix, AZ 85034
Tel: (602) 437-9492
Fax: (602) 437-9435
E-mail: [email protected]
Web: http://www.elvisions.com
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Hi Xiaochuan Zhou,
it is certainly difficult to apply resist onto a wafer with deep structures.
Even if you succeed with this (spray resist, resist lamination) the
structures
may become less accurate. There is a trick though which works with some
structures:
Do all the lithos one after the other BEFORE deep etching. Then, after each
deep
etching step, remove one layer of resist with dry etching. This resist
stripping
must be quite accurate, of course.
Please let me know about your solution and results.
Thank you,
Ralf G. Longwitz.
Research Assistant
Microsystems integration group
Swiss Fed. Inst. of Technology
_______________________________
EPFL-DMT-IMS BM 3.125
http://dmtwww.epfl.ch/~rlongwit
Tel: +41.21-693 6727
Fax: +41.21-693 5950
_______________________________
__________________________________________________
Xiaochuan Zhou,
I have some experience in multi-level anisotropic etching and in working
with 110 wafers. I would be pleased to chat with you but it may be
easier to do by phone so that I could understand your needs better. In
particular, I don't think the 110 wafer approach will work well for
through-holes. This approach works well for slits (sort of like a
venetion blind) where the vertical planes are required on two sides, not
four. The other two side planes have significant slopes.
You can contact me at 780-492-3914
Graham McKinnon
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Dr. Zhou,
Best results are going to be by using RIE
(reactive ion etching) and preferably
DRIE (deep reactive ion etching)..... instead
of KOH etches. However, KOH can be used for
at least your 10 micron deep basins.
Steps:
(1) Coat wafer with RIE photoresist on front side
(2) Expose to Mask #1 (this mask only has
the 10 micron deep basins patterned into it)
(3) Develop
(4) RIE or KOH etch the 10 micron basins
(5) Remove photoresist
(6) Coat wafer front side with more RIE photoresist
(this resist is quite thick, and should conformally
cover the 10 micron step at the edges of the basins
with no problem)
(7) Expose to Mask #2 (this mask has the 50 micron
deep trenches patterned into in... with alignment
marks for registration). Align using infra red
to see through the photoresist
(8) Develop
(9) DRIE the 50 micron deep trenches
(10) Remove photoresist
(11) Coat back side of wafer with RIE photoresist
(12) Expose to Mask #3 (this mask has only the
narrow through-holes patterned into it..... with
infra red alignment marks)
(13) Develop
(14) DRIE the through-holes from the back side
(15) Remove photoresist
(16) You're done!
Good luck,
brian hubert, micromedia, mit media laboratory
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Xiaochuan,
you can try to do a multi-stage oxidation. you will still have a small
step height that may cause problems with spinning resist but it will be
reduced. there is also a type of photoresist that is sputterable which
is a better solution, but I do not have specific info on this. for the
oxidation you can do...
1. oxidation
2. pattern structure A
3. oxidation
4. pattern structure B
5. oxidation
6. pattern structure C
this will leave no oxide on structure C, 1 layer on structure B, 2
layers on structure A, and 3 layers everywhere else. it requires careful
etching of the oxide to stop at the right time and I would keep each
layer about 0.1um thick at the most. at lower temps, koh is more
selective between oxide and silicon. I have done room temp koh etches
150um deep while consuming about 0.1um of oxide. you may try doing the
two shallow structures this way and getting the through holes with deep
rie.
Chris Foreman
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Xiaochuan:
Have you heard of closed cover spinning processes?
These have been designed for exactly the problems you have described. The
trick is to maintain a solvent saturated dispense and spin environment to
help evenly distribute the resist over extreme topography.
Karl Suss patented the rotating closed cover process some years ago.
If you tell me where you're located I'll have one of our coating application
engineers get hold of you and see if they can help you out, either with some
sample runs or perhaps some process help. They have significant experience
with MEMS devices and both open and closed cover spinning processes.
Regards,
Jim
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Xiaochuan Zhou-
I am with Delphi Automotive's MEMS group in Indiana. Even though I can't
tell what your structure is from your decription, I can give you some
ideas.
First, you should be able to mask with photoresist when you have 10 micron
steps if the steps are formed by a SF6 dry etch (60-70 degree sidewalls) or
by using a KOH etch on (100) wafers (54.7 degree sidewalls). We have done
this many times.
I have seen successful photolithography with deep trenches when multiple
layers of resist are used. This is not my expertise and I would not
suggest this for production.
Assuming that you can live with the 10 micron steps, the 50 micron deep 50
micron wide trenches can be formed with DRIE. This is a dry etch with
straight sidewalls. U of M has experience with this and you can get it
done on the outside. DRIE could also be used from the backside of the
wafer to make the through holes. This is a manufacturable process but it
will take a long time to get through the wafers (4-8 microns/minute). We
generally limit this type of etch to less than 50 microns in order to
increase our throughput in production.
__________________________________________________
Using thin film resists that PCB board manufacturers use may be one option.
shekhar
__________________________________________________
Hi Xiaochuan Zhou,
it is certainly difficult to apply resist onto a wafer with deep structures.
Even if you succeed with this (spray resist, resist lamination) the
structures
may become less accurate. There is a trick though which works with some
structures:
Do all the lithos one after the other BEFORE deep etching. Then, after each
deep
etching step, remove one layer of resist with dry etching. This resist
stripping
must be quite accurate, of course.
Please let me know about your solution and results.
Thank you,
Ralf G. Longwitz.
Research Assistant
Microsystems integration group
Swiss Fed. Inst. of Technology
_______________________________
EPFL-DMT-IMS BM 3.125
http://dmtwww.epfl.ch/~rlongwit
Tel: +41.21-693 6727
Fax: +41.21-693 5950
_______________________________
__________________________________________________
Dear Xiaochuan Zhou,
for a two-step etching I use a dynamic mask (oxide) which is controlled
etched in KOH. However, for a three-step etch it might not be the best
solution. What I would suggest is to use an electrodepositable photoresist
to pattern the etch masks for step two and three. I would recommend
Shipley's Eagle 2100 ED/PR. Although this resist is stable in KOH it does
not adhere very well to the resist plating base. Since you anyway need a
plating base for the resist you should also use this plating base as etch
mask. The Eagle resist can be deposited on all kind of metals (Al is
somewhat difficult). I would go for Au or Ni. If you need any more info on
the ED photoresist do not hesitate to contact me.
Best regards,
Matthias
________________________________________________________________
Matthias Heschel, PhD
Assistant Research Professor, MEMS
--------------------------------------
Microelectronics Center
Technical University of Denmark, Bldg. 345 east
DK-2800 Lyngby
