Regan,

I've heard that silicon wafers are not totally flat on the 1-0-0
crystalline surface because a skew is introduced deliberately to
prevent tunneling during ion implantation. Is it possible that
your etch depth differentiation be due to that factor?
If that is true, time etch without p++ doping would not give you
the depth uniformity you want.


Patrick Cheung, research scientist   Xerox PARC, MS 35-1674
(O) 650-812-4338 (FAX) 650-812-4719   3333 Coyote Hill Road
[email protected]                  Palo Alto, CA 94304
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On Wed, 27 Jan 1999 [email protected] wrote:

Dear colleagues,

I am working on etching Si in KOH until 5 to 10um is left without
using P++ doping.But I have observed a 7um etching depth
difference between the OF side and it's opposite side. And an
almost 20um difference in the maximum and minimum etching depth
measured within the wafer.

I tried a bubbler within the etching bath but the resulting
etching distribution was almost the same as before.

I am wondering if there are other ways of obtaining a good KOH
etching distribution.Any idea and suggestions will be greatly
appreciated.

Regan Nayve
[email protected]

****************************************
Etching condition
KOH           : 15% 90C
Temp control  :  $B!^ (B1C
Etching bath  : Stainless(with top cover)
Bath dimension: L20 W23 H23  (cm)