Dear MEMS community,

I'd like to know if the upper layer of an SOI wafer (5µm Si - 1µm SiO2 -
525µm Si) could be under compressive stress condition (induced by the
fabrication process).

thanks
regards

Matth
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     Matthieu GUIRARDEL
   7, av du colonel Roche
   31077 TOULOUSE Cedex 4

           [email protected]

         (+33) 5 61 33 63 51

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