Dear Alexander Hoelke,
Yes, I agree with you. The problem at 110 silicon is, that the flat
direction is not standardised. So you can get  all directions for your
vertical 111-faces. The point of interesting is that the vertical
planes occurs at a tetragon with the angles of 109.5 and 70.5.


With kind regards
Dirk Zielke





> Date:          Thu, 27 Aug 1998 10:19:21 -0400
> From:          Alexander Hoelke 
> Organization:  Universtity of Cincinnati
> To:            Dirk Zielke , [email protected]
> Subject:       Re: (Fwd) FW: deep vertical KOH etching

>
>
> > >  I have worked the acceleration sensor.
> > >  My questions are
> > >  1. the method of vertical KOH etching on (110) Si wafer.
> > >  2. the etching rate of vertical KOH etching on (110) Si wafer.
> > >  I wish your advices and informations.
> > >  Thank you so much for reading my mail.
> > >  e-mail address; [email protected]
> >
> > Hi,
> > The vertical trenches are only produced  on two direction. These are
> > 35.26° and 144.73 degree, if the flat is in 110-direction. The etch
> > rates of the 111-planes are nearby zero, if you hit exactly the
> > directions (mask misalignment). Furthermore is the design of such
> > structures more complicate compared with 100-silicon, because of the
> > non existing 8-times symmetry of 110-silicon.
> > Dirk Zielke
>
> Also, there is no standard for flats on (110) wafers. My understanding is,
> if the flat is along a <110> direction, and there is only one on a (110)
> wafer,  and if you align a pattern parallel to that, you get a shallow
> v-groove, consisting of two {111} planes. The vertically intersecting (111)
> planes you are looking for are then at 54.74 and 125.26 off that flat.
>
> The case Mr. Zielke is describing is that the flat is along a <100>
> direction, I believe. There is, again, also only one <100> direction lying
> in a (110) surface, and the <110> direction I was referring to first is
> perpendicular to that. We used to have wafers like that  a long time ago,
> mask design is complicated.
>
> Another thing makes alignment difficult: Front- and backside are unique. If
> you want to use both directions that produce vertical channels, you have to
> make sure which side of the wafer you are. The corresponding patterns that
> you need for either side are the mirror images of each other.
>
> We now use (110) wafers with two flats. These are the dirctions of the
> vertically intersecting {111} planes. These directions are of type <112>,
> and I have not found that mentioned anywhere in the literature (except in a
> paper I am trying to publish for some time now). Anyway, that makes mask
> design much simpler, especially if you are only interested in exposing
> vertical {111} planes in one direction, such as in the case of etching
> narrow channels. Then, it also doesn't matter which side of the wafer you
> use. If it does, you can tell relatively easily.
>
> Virginia Semiconductor is our wafer supplier.
>
> Good luck
>
>
>
>
Dirk Zielke
GEMAC mbH
Matthesstrasse 53
09113 Chemnitz
Germany
Tel.: +49 371 3377 131
Fax.: +49 371 3377 272
email: [email protected]
http://gemac.c.ntg.de (Deutsch)
http://gemac.c.ntg.de/mst_eng.htm (English)